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low power, 16-bit buffered sigma-delta adc ad7790 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent ri ghts of analog devices. trademarks and registered trademarks are the proper ty of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.326.8703 ? 2003 analog devices, inc. all rights reserved. features power supply: 2.5 v to 5.25 v operation normal: 75 a maximum power-down: 1 a maximum rms noise: 1.1 v at 9.5 hz update rate 16-bit p-p resolution integral nonlinearity: 3.5 ppm typical simultaneous 50 hz and 60 hz rejection internal clock oscillator programmable gain amplifier rail-to-rail input buffer v dd monitor channel temperature range: C40c to +105c 10-lead msop interface 3-wire serial spi?, qspi?, microwire?, and dsp compatible schmitt trigger on sclk applications smart transmitters battery applications portable instrumentation sensor measurement temperature measurement pressure measurement weigh scales 4 to 20 ma loops functional block diagram 03538-0-001 serial interface internal clock 16-bit adc a in gnd refin ad7790 v dd digital pga buf v dd gnd figure 1. general description the ad7790 is a low power, complete analog front end for low frequency measurement applications. it contains a low noise 16-bit -? adc with one differential input that can be buffered or unbuffered along with a digital pga, which allows gains of 1, 2, 4, and 8. the device operates from an internal clock. therefore, the user does not have to supply a clock source to the device. the output data rate from the part is software programmable and can be varied from 9.5 hz to 120 hz, with the rms noise equal to 1.1 v at the lower update rate. the internal clock frequency can be divided by a factor of 2, 4, or 8, which leads to a reduc- tion in the current consumption. the update rate, cutoff frequency, and settling time will scale with the clock frequency. the part operates with a power supply from 2.5 v to 5.25 v. when operating from a 3 v supply, the power dissipation for the part is 225 w maximum. it is housed in a 10-lead msop.
ad7790 rev. 0 | page 2 of 20 table of contents ad7790?specifications.................................................................. 3 timing characteristics..................................................................... 5 absolute maximum ratings............................................................ 7 pin configuration and function descriptions............................. 8 typical performance characteristics ............................................. 9 on-chip registers .......................................................................... 10 communications register (rs1, rs0 = 0, 0) ......................................................................... 10 status register (rs1, rs0 = 0, 0; power-on/reset = 0x88)............................... 11 mode register (rs1, rs0 = 0, 1; power-on/reset = 0x02)............................... 11 filter register (rs1, rs0 = 1, 0; power-on/reset = 0x04)............................... 12 data register (rs1, rs0 = 1, 1; power-on/reset = 0x0000) .......................... 12 adc circuit information.............................................................. 13 overview ..................................................................................... 13 noise performance ..................................................................... 13 reduced current modes ........................................................... 13 digital interface .......................................................................... 14 single conversion mode ....................................................... 15 continuous conversion mode............................................. 15 continuous read mode ........................................................ 16 circuit description......................................................................... 17 analog input channel ............................................................... 17 programmable gain amplifier................................................. 17 bipolar configuration................................................................ 17 data output coding .................................................................. 17 reference input........................................................................... 17 v dd monitor ................................................................................ 18 grounding and layout .............................................................. 18 outline dimensions ....................................................................... 19 revision history revision 0: initial version
ad7790 rev. 0 | page 3 of 20 ad7790?specifications 1 table 1. (v dd = 2.5 v to 5.25 v; refin(+) = 2.5 v; refin(C) = gnd; cdiv1 = cdiv0 = 0; gnd = 0 v; all specifications t min to t max , unless otherwise noted.) parameter ad7790b unit test conditionscomments adc cannel specification output update rate 9.5 min nom 120 max nom adc cannel no missing codes 2 16 bits min v ref range, update rate
ad7790 rev. 0 | page 4 of 20 specifications (continued) 1 parameter ad7790b unit test conditions/comments reference input (continued) normal mode rejection 2 @ 50 hz, 60 hz 65 db min 73 db typ, 50 1 hz, 60 1 hz, fs[2:0] = 100 4 @ 50 hz 80 db min 90 db typ, 50 1 hz, fs[2:0] = 101 4 @ 60 hz 80 db min 90 db typ, 60 1 hz, fs[2:0] = 011 4 common mode rejection input range = 2.5 v, ain = 1 v @ dc 100 db typ fs[2:0] = 100 4 @ 50 hz, 60 hz 110 db typ 50 1 hz (fs[2:0] = 101 4 ), 60 1 hz (fs[2:0] = 011 4 ) logic inputs all inputs except sclk 2 v inl , input low voltage 0.8 v max v dd = 5 v 0.4 v max v dd = 3 v v inh , input high voltage 2.0 v min v dd = 3 v or 5 v sclk only (schmitt-triggered input) 2 v t (+) 1.4/2 v min/v max v dd = 5 v v t (?) 0.8/1.4 v min/v max v dd = 5 v v t (+) ? v t (?) 0.3/0.85 v min/v max v dd = 5 v v t (+) 0.9/2 v min/v max v dd = 3 v v t (?) 0.4/1.1 v min/v max v dd = 3 v v t (+) - v t (?) 0.3/0.85 v min/v max v dd = 3 v input currents 1 a max v in = v dd or gnd input capacitance 10 pf typ all digital inputs logic outputs v oh , output high voltage 2 v dd ? 0.6 v min v dd = 3 v, i source = 100 a v ol , output low voltage 2 0.4 v max v dd = 3 v, i sink = 100 a v oh , output high voltage 2 4 v min v dd = 5 v, i source = 200 a v ol , output low voltage 2 0.4 v max v dd = 5 v, i sink = 1.6 ma floating-state leakage current 1 a max floating-state output capa citance 10 pf typ data output coding offset binary power requirements 5 power supply voltage v dd ? gnd 2.5/5.25 v min/max power supply currents i dd current 6 75 a max 65 a typ, v dd = 3.6 v, unbuffered mode 145 a max 130 a typ, v dd = 3.6 v, buffered mode 80 a max 73 a typ, v dd = 5.25 v, unbuffered mode 160 a max 145 a typ, v dd = 5.25 v, buffered mode i dd (power-down mode) 1 a max 5 digital inputs equal to v dd or gnd. 6 the current consumption can be further reduced by using the adc in one of the low power modes (see table 15).
ad7790 rev. 0 | page 5 of 20 timing characteristics 1, 2 table 2. (v dd = 2.5 v to 5.25 v; gnd = 0 v, refin(+) = 2.5 v, refi n(C) = gnd, cdiv1 = cdiv0 = 0, input logic 0 = 0 v, input logic 1 = v dd , unless otherwise noted.) parameter limit at t min , t max (b version) unit conditionscomments t 3 100 ns min scl igh pulsewidth t 4 100 ns min scl low pulsewidth read operation t 1 0 ns min cs falling edge to doutrd active time 60 ns max v dd = 4.75 v to 5.25 v 80 ns max v dd = 2.5 v to 3.6 v t 2 3 0 ns min scl active edge to data valid delay 4 60 ns max v dd = 4.75 v to 5.25 v 80 ns max v dd = 2.5 v to 3.6 v t 5 5, 6 10 ns min bus relinuish time after cs inactive edge 80 ns max t 6 100 ns max scl inactive edge to cs inactive edge t 7 10 ns min scl inactive edge to doutrd igh rite operation t 8 0 ns min cs falling edge to scl active edge setup time 4 t 9 30 ns min data valid to scl edge setup time t 10 25 ns min data valid to scl edge old time t 11 0 ns min cs rising edge to scl edge old time 1 sample tested during initial release to ensure compliance. all input signals are specified with t r = t f = 5 ns (10 to 90 of v dd ) and timed from a voltage level of 1.6 v. 2 see figure 3 and figure 4. 3 these numbers are measured with the load circuit of figure 2 and defined as the time reuired for the output to cross the v ol or v o limits. 4 scl active edge is falling edge of scl. 5 these numbers are derived from the measured time taken by the data output to change 0.5 v when loaded with the circuit of figu re 2. the measured number is then extrapolated back to remove the effects of charging or discharging the 50 pf capacitor. this means that the times uoted in the timing characteristics are the true bus relinuish times of the part and, as such, are independent of external bus loading capacitances. 6 rd returns high after a read of the adc. in single conversion mode and continuous conversion mode, the same data can be read agai n, if reuired, while rd is high, although care should be taken to ensure that subseuent reads do not occur close to the next output update. in continuous read mode, the digital word can be read only once.
ad7790 rev. 0 | page 6 of 20 03538-0-002 i sink (1.6ma with v dd = 5v, 100
ad7790 rev. 0 | page 7 of 20 absolute maximum ratings table 3. (t a = 25c, unless otherwise noted.) parameter rating v dd to gnd C0.3 v to +7 v analog input voltage to gnd C0.3 v to v dd + 0.3 v reference input voltage to gnd C0.3 v to v dd + 0.3 v total ainrefin current (indefinite) 30 ma digital input voltage to gnd C0.3 v to v dd + 0.3 v digital output voltage to gnd C0.3 v to v dd + 0.3 v operating temperature range C40c to +105c storage temperature range C65c to +150c maximum unction temperature 150c msop a thermal impedance
ad7790 rev. 0 | page 8 of 20 pin configuration and fu nction descriptions 03538-0-005 ad7790 top view (not to scale) sclk 1 cs 2 ain(+) 3 ain(?) 4 ref(+) 5 din dout/rdy v dd gnd ref(?) 10 9 8 7 6 figure 5. pin configuration table 4. pin function descriptions pin no. mnemonic function 1 scl serial clock input for data transfers to and from the adc. the scl has a schmitt- triggered input, making the interface suitable for opto-isolated applications. the serial clock can be continuous with all data transmitted in a continuous train of pulses. alternatively, it can be a noncontinuous clock with the information being trans- mitted to or from the adc in smaller batches of data. 2 cs chip select input. this is an active low logic input used to select the adc. cs can be used to select the adc in systems with more than one device on the serial bus or as a frame synchroniation signal in communi- cating with the device. cs can be hardwired low, allowing the adc to operate in 3-wire mode with scl, din, and dout used to interface with the device. 3 ain(+) analog input. ain(+) is the positive terminal of the fully differential analog input. 4 ain(C) analog input. ain(C) is the negative termi- nal of the fully differential analog input. 5 refin(+) positive reference input. refin(+) can lie anywhere between v dd and gnd + 0.1 v. the nominal reference voltage (refin(+) C refin(C)) is 2.5 v, but the part functions with a reference from 0.1 v to v dd . pin no. mnemonic function 6 refin(C) negative reference input. this reference input can lie anywhere between gnd and v dd C 0.1 v. 7 gnd ground reference point. 8 v dd supply voltage, 2.5 v to 5.25 v. 9 doutrd serial data output data ready output. doutrd serves a dual purpose. it functions as a serial data outp ut pin to access the out- put shift register of the adc. the output shift register can contain data from any of the on- chip data or control registers. in addition, doutrd operates as a data ready pin, going low to indicate the completion of a conversion. if the data is not read after the conversion, the pin will go high before the next update occurs. the doutrd falling edge can be used as an interrupt to a processor, indicating that valid data is available. ith an external serial clock, the data can be read using the doutrd pin. ith cs low, the datacontrol word informa- tion is placed on the doutrd pin on the scl falling edge and is valid on the scl rising edge. the end of a conversion is also indicated by the rd bit in the status register. hen cs is high, the doutrd pin is three-stated but the rd bit remains active. 10 din serial data input to th e input shift register on the adc. data in this shift register is transferred to the control registers within the adc, the register selection bits of the communications register identifying the appropriate register.
ad7790 rev. 0 | page 9 of 20 typical performance characteristics 03538-0-007 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 04080 20 60 100 120 140 db 160 0 frequency (hz) figure 6. frequency response for a 16.6 hz update rate 03538-0-013 0 0.5 1.0 1.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 rms noise (
ad7790 rev. 0 | page 10 of 20 on-chip registers the adc is controlled and configured via a number of on-chip registers, which are described on the following pages. in the foll owing descriptions, set lesaocstatead cleared lesaocstatelessotersestated cnicainregierrr ecocatosrestersatrteolresterallcocatostoteartststarttarteoeratot oteco catosresteredatarttetotecocatosresterdetereseterteetoeratosareadorrte oerato adtocrestertsoeratotaeslaceforreadorrteoeratosocetesseetreadorrteoeratoto teselected resterscoleteteteraceretrstoereteectsarteoeratototecocatosresterssted ealtstateo teteraceadooerorateraresetteacstsdealtstateatorarteoeratototecoc atosres teristatosereteteraceseeceslostarteoeratooatleastseralcloccclestinret rsteacto tsdealtstateresettteetreartaleotlestetdesatosortecocatosrestercrtr ocrd catetetlocatocrdeottetsaretecocatosrestercrdeotestersttotedatastrea eer racetsdcatesteoeroresetdealtstatsotatt crcrcrcrcrcrcrcr en r r r crea c c table 5. communications register bit designations bit location bit name description cr7 en rite enable bit. a 0 must be written to this bit so that the write to the communications register actually occurs. if a 1 is the first bit written, the part will not cl ock on to subseuent bits in the register. it will stay at this bit location until a 0 is written to this bit. once a 0 is written to the en bit, the next seven bits will be loaded to the communications register. cr6 0 this bit must be programmed to logic 0 for correct operation. cr5Ccr4 rs1Crs0 register address bits. these address bits are used to select which of the adcs registers are being selected during this serial interface communication. see table 6. cr3 r a 0 in this bit location indicates that the next operati on will be a write to a specified register. a 1 in this position indicates that the next operation will be a read from the designated register. cr2 cread continuous read of the data registe r. hen this bit is set to 1 (and th e data register is selected), the serial interface is configured so th at the data register can be continuo usly read, i.e., the contents of the data register are placed on the dout pin automati cally when the scl pulses are applied. the commu- nications register does not have to be written to fo r data reads. to enable continuous read mode, the instruction 001111xx must be written to the communica tions register. to exit the continuous read mode, the instruction 001110xx must be written to the communications register while the rd pin is low. hile in continuous read mode , the adc monitors activity on the di n line so that it can receive the instruction to exit continuous read mode. additionally, a reset will occur if 32 consecutive 1s are seen on din. therefore, din should be held low in continuous read mode until an instruction is to be written to the device. cr1Ccr0 c1Cc0 these bits are used to select the analog input channel. the differential channel can be selected (ain(+)ain(C)) or an internal short (ain(C)ain(C)) can be selected. alternatively, the power supply can be selected, i.e., the adc can measure the voltage on the power supply, which is useful for monitoring power supply variation. the power su pply voltage is divided by 5 and then applied to the modulator for conversion. the adc uses a 1.17 v 5 on-chip refe rence as the reference source for the analog to digital conversion. any change in channel resets the filter and a new conversion is started. table 6. register selection rs1 rs0 register register sie 0 0 communications register during a rite operation 8-bit 0 0 status register during a read operation 8-bit 0 1 mode register 8-bit 1 0 filter register 8-bit 1 1 data register 16-bit table 7. channel selection c1 c0 channel 0 0 ain(+) C ain(C) 0 1 reserved 1 0 ain(C) C ain(C) 1 1 v dd monitor
ad7790 rev. 0 | page 11 of 20 status register (rs1, rs0 = 0, 0; power-on/reset = 0x88) the status register is an 8-bit read-only register. to access the adc status register, the user must write to the communication s register, select the next operation to be a read, and load bits rs1 and rs0 with 0. table 8 outlines the bit designations for the status register. sr0 through sr7 indicate the bit locations, sr denoting the bits are in the status register. sr7 denotes the first bit of the data stream. the number in brackets indicates the power-on/reset default status of that bit. sr7 sr6 sr5 sr4 sr3 sr2 sr1 sr0 rdy (1) err(0) 0(0) 0(0) 1(1) wl(0) ch1(0) ch0(0) table 8. status register bit designations bit location bit name description sr7 rd ready bit for adc. cleared when data is written to th e adc data register. the rd bit is set automatically after the adc data register has been read or a period of time before the data re gister is updated with a new conversion result to indicate to the user not to read the conversi on data. it is also set when the part is placed in powe-down mode. the end of a conversion is indicated by the doutrd pin also. this pin can be used as an alternative to the status register for monitori ng the adc for conversion data. sr6 err adc error bit. this bit is written to at the same time as the rd bit. set to indicate that the result written to the adc data register has been clamped to al l 0s or all 1s. error sources include overrange, underrange. cleared by a write operation to start a conversion. sr5 0 this bit is automatically cleared . sr4 0 this bit is automatically cleared . sr3 1 this bit is automatically set . sr2 0 this bit is automatically cleared if the device is an ad7790. it can be used to distinguish between the ad7790 and ad7791, in which the bit is set . sr1Csr0 c1Cc0 these bits indicate which channel is being converted by the adc. mode register (rs1, rs0 = 0, 1; poer-onreset = 0x02) the mode register is an 8-bit register from which data can be read or to which data can be written. this register is used to co nfigure the adc for range, enable or disable the buffer, or place the device into power-down mode. table 9 outlines the bit designations fo r the mode register. mr0 through mr7 indicate the bit locations, mr denoting the bits are in the mode register. mr7 denotes the first bit of the data stream. the number in brackets indicates the power-onreset default status of that bit. any write to the setup register resets the modulator and filter and sets the rd bit. mr7 mr6 mr5 mr4 mr3 mr2 mr1 mr0 md1(0) md0(0) g1(0) g0(0) bo(0) 0(0) buf(1) 0(0) table 9. mode register bit designations bit location bit name description mr7Cmr6 md1Cmd0 mode select bits. these bits select between contin uous conversion mode, single conversion mode, and standby mode. in continuous conver sion mode, the adc continuously performs conversions and places the result in the data register. rd goes low when a conversion is complete. the user can read these conversions by placing the device in continuous re ad mode whereby the conv ersions are automatically placed on the dout line when scl pulses are applie d. alternatively, the user can instruct the adc to output the conversion by writing to the communication s register. after power-on, the first conversion is available after a period 2 f adc while subseuent conversions are available at a freuency of f adc . in single conversion mode, the adc is placed in power-down mode when conversions are not being performed. hen single conversion mode is selected, the adc powers up and performs a single conversion, which occurs after a period 2f adc . the conversion result in placed in the data register, rd goes low, and the adc returns to power-down mode. the conversi on remains in the data register and rd remains active (low) until the data is read or another conversion is performed. see table 10. mr5Cmr4 g1Cg0 range bits. the ad7790 can be operate d with four analog inp ut ranges (see table 11). mr3 bo burnout current enable bit. hen this bit is set to 1 by the user, the 100 na current sources in the signal path are enabled. hen bo = 0, the burnout curren ts are disabled. the burnout currents can be enabled only when the buffer is active.
ad7790 rev. 0 | page 12 of 20 bit location bit name description mr2 0 this bit must be programmed with a logic 0 for correct operation. mr1 buf configures the adc for buffered or unbuffered mode of operation. if cleared , the adc operates in unbuffered mode, lowering the power consumption of the device. if set , the adc operates in buffered mode, allowing the user to place source impedances on the front end without co ntributing gain errors to the system. mr0 0 this bit must be programmed with a logic 0 for correct operation. table 10. operating modes md1 md0 mode 0 0 continuous conversion mode (default) 0 1 reserved 1 0 single conversion mode 1 1 power-down mode table 11. analog input ranges g1 g0 range ad7790 lsb sie with v ref = +2.5 v (v) 0 0 v ref 76.3 0 1 v ref 2 38.14 1 0 v ref 4 19.07 1 1 v ref 8 9.54 filter register (rs1, rs0 = 1, 0; poer-onreset = 0x04) the filter register is an 8-bit register from which data can be re ad or to which data can be written. this register is used to set the output word rate. table 12 outlines the bit designations for the filter register. fr0 through fr7 indicate the bit locations, fr denoting t he bits are in the filter register. fr7 denotes the first bit of the data stream. the number in brackets indicates the power-onreset default stat us of that bit. fr7 fr6 fr5 fr4 fr3 fr2 fr1 fr0 0(0) 0(0) cdiv1(0) cdiv0(0) 0(0) fs2(1) fs1(0) fs0(0) table 12. filter register bit designations bit location bit name description fr7Cfr6 0 these bits must be programmed with a logic 0 for correct operation. fr5Cfr4 cldiv1C cdiv0 these bits are used to operate the ad7790 in the lowe r power modes. the clock is internally divided and the power is reduced. 00 normal mode 01 clock divided by 2 10 clock divided by 4 11 clock divided by 8 fr3 0 this bit must be programmed with a logic 0 for correct operation. fr2Cfr0 fs2Cfs0 these bits set the output word rate of the adc. the update rate influe nces the 50 60 reection and noise. the noise is the same for all gain settings. s ee table 13 for the allowable update rates in full power mode. in the low power modes, the update rates will be reduce d. (see reduced current modes.) table 13. update rates fs2 fs1 fs0 f adc () f3db () rms noise (v) reection 0 0 0 120 28 40 25 db 60 0 0 1 100 24 25 25 db 50 0 1 0 33.3 8 3.36 0 1 1 20 4.7 1.6 80 db 60 1 0 0 16.6 4 1.5 65 db 50 60 (default setting) 1 0 1 16.7 4 1.5 80 db 50 1 1 0 13.3 3.2 1.2 1 1 1 9.5 2.3 1.1 62 db 5060 data register (rs1, rs0 = 1, 1; poer-onreset = 0x0000) the conversion result from the adc is stored in this data register. this is a read-only register. on completion of a read opera tion from this register, the rd bitpin is set.
ad7790 rev. 0 | page 13 of 20 adc circuit information overview the ad7790 is a low power adc that incorporates a - modulator, a buffer, a pga, and on-chip digital filtering intend- ed for the measurement of wide dynamic range, low frequency signals such as those in pressure transducers, weigh scales, and temperature measurement applications. the part has one differential input that can be buffered or unbuffered. buffering the input channel means that the part can accommodate significant source impedances on the analog input and that r, c filtering (for noise rejection or rfi reduc- tion) can be placed on the analog input, if required. the device requires an external reference of 2.5 nominal. figure 7 shows the basic connections required to operate the part. 03538-0-006 in+ 10 table 14. typical peak-to-peak resolution (effective resolution) vs. update rate and input range input range update rate 0.3125 0.625 1.25 2.5 9.5 16 (16) 16 (16) 16 (16) 16 (16) 13.3 16 (16) 16 (16) 16 (16) 16 (16) 16.7 16 (16) 16 (16) 16 (16) 16 (16) 16.6 16 (16) 16 (16) 16 (16) 16 (16) 20 15.5 (16) 16 (16) 16 (16) 16 (16) 33.3 14.5 (16) 15.5 (16) 16 (16) 16 (16) 100 11.5 (14) 12.5 (15) 13.5 (16) 14.5 (16) 120 11 (13.5) 12 (14.5) 13 (15.5) 14 (16) reduced current modes the ad7790 has a current consumption of 160 a maximum when operated with the buffer enabled and with a 5 v power supply. the power can be reduced further by setting bits cdiv1 and cdiv0 in the filter register appropriately (see table 15). by setting these bits, the internal clock is divided by 2, 4, or 8 before being applied to the modulator and filter, resulting in a reduction in the digital current. hen the internal clock is reduced, the update rate will also be reduced. for example, if the filter bits are set to give an update rate of 16.6 when the ad7790 is operated in full clock mode, the update rate will eual 8.3 in divide by 2 mode. in these low power modes, there may be some degradation in the adc performance. table 15. low power mode selection cdiv10 clock typ current, buffered (a) typ curr ent, unbuffered (a) 50 60 reection (db) 00 1 146 75 70 10 12 87 45 72 10 14 56 30 88 11 18 41 25 89
ad7790 rev. 0 | page 14 of 20 digital interface as previously outlined, the ad7790?s programmable functions are controlled using a set of on-chip registers. data is written to these registers via the part?s serial interface and read access to the on-chip registers is also provided by this interface. all com- munications with the part must start with a write to the communications register. after power-on or reset, the device expects a write to its communications register. the data written to this register determines whether the next operation is a read operation or a write operation and also determines to which register this read or write operation occurs. therefore, write access to any of the other registers on the part begins with a write operation to the communications register followed by a write to the selected register. a read operation from any other register (except when continuous read mode is selected) starts with a write to the communications register followed by a read operation from the selected register. the ad7790?s serial interface consists of four signals: cs , din, sclk, and dout/ rdy . the din line is used to transfer data into the on-chip registers while dout/ rdy is used for access- ing from the on-chip registers. sclk is the serial clock input for the device and all data transfers (either on din or dout/ rdy ) occur with respect to the sclk signal. the dout/ rdy pin operates as a data ready signal also, the line going low when a new data-word is available in the output register. it is reset high when a read operation from the data register is complete. it also goes high prior to the updating of the data register to indicate when not to read from the device to ensure that a data read is not attempted while the register is being updated. cs is used to select a device. it can be used to decode the ad7790 in systems where several components are connected to the serial bus. figure 3 and figure 4 show timing diagrams for interfacing to the ad7790 with cs being used to decode the part. figure 3 shows the timing for a read operation from the ad7790?s output shift register while figure 4 shows the timing for a write opera- tion to the input shift register. in all modes except continuous read mode, it is possible to read the same word from the data register several times even though the dout/ rdy line returns high after the first read operation. however, care must be taken to ensure that the read operations have been completed before the next output update occurs. in continuous read mode, the data register can be read only once. the serial interface can operate in 3-wire mode by tying cs low. in this case, the sclk, din, and dout/ rdy lines are used to communicate with the ad7790. the end of the conversion can be monitored using the rdy bit in the status register. this scheme is suitable for interfacing to microcontrollers. if cs is required as a decoding signal, it can be generated from a port pin. for microcontroller interfaces, it is recommended that sclk idles high between data transfers. the ad7790 can be operated with cs being used as a frame synchronization signal. this scheme is useful for dsp interfaces. in this case, the first bit (msb) is effectively clocked out by cs since cs would normally occur after the falling edge of sclk in dsps. the sclk can continue to run between data transfers, provided the timing numbers are obeyed. the serial interface can be reset by writing a series of 1s on the din input. if a logic 1 is written to the ad7790 line for at least 32 serial clock cycles, the serial interface is reset. this ensures that in 3-wire systems, the interface can be reset to a known state if the interface gets lost due to a software error or some glitch in the system. reset returns the interface to the state in which it is expecting a write to the communications register. this operation resets the contents of all registers to their power- on values. the ad7790 can be configured to continuously convert or to perform a single conversion. see figure 8 through figure 10.
ad7790 rev. 0 | page 15 of 20 single conversion mode n single onversion ode te is laed in sutdon ode eteen onversions en a single onversion is initi ated setting m to and m to in te ode register te oers u erors a single onversion and ten returns to sutdon ode onversion ill reuire a tie eriod o t c r goes lo to indiate te o letion o a onversion en te dataord as een read ro te data register r ill go ig cs is lo r ill reain ig until anoter onversion is initi ated and oleted e data register an e read several ties i reuired even en r as gone ig continuous conversion mode is is te deault oeru ode e ill ontinu ousl onvert te r in in te status register going lo ea tie a onversion is olete cs is lo te r line ill also go lo en a onversion is olete o read a on version te user an rite to te ouniations register indiating tat te net oeration is a read o te data register e digital onversion ill e laed on te r in as soon as sc ulses are alied to te c r ill return ig en te onversion is read e user an read tis register additional ties i reuired oever te user ust ensure tat te data register is not eing aessed at te ole tion o te net onversion or else te ne onversion ord ill e lost sc r cs igure single conversion sc r cs igure continuous conversion
ad7790 rev. 0 | page 16 of 20 continuous read mode rater tan rite to te ouniations register ea tie a onversion is olete to aess te data te an e laed in ontinuous read ode riting to te ouniations register te user onl needs to al te aroriate nuer o sc les to te c and te it ord ill autoatiall e laed on te r line en a onversion is olete en r goes lo to indiate te end o a onver sion suiient sc les ust e alied to te c and te data onversion ill e laed on te r line en te onversion is read r ill return ig until te net onversion is availale n tis ode te data an e read onl one lso te user ust ensure tat te dataord is read eore te net onversion is olete te user as not read te onversion eore te oletion o te net onversion or i insuiient serial los are alied to te to read te ord te serial outut register is reset en te net onver sion is olete and te ne onversion is laed in te outut serial register o eit te ontinuous read ode te instrution ust e ritten to te ouniations register ile te r in is lo ile in te ontinuous read ode te c onitors ativit on te line so tat it an reeive te instrution to eit te ontinuous read ode dditionall a reset ill our i onseutive s are seen on ereore sould e eld lo in ontinuous read ode until an instrution is to e ritten to te devie sc r cs c igure continuous read
ad7790 rev. 0 | page 17 of 20 circuit description analog input channel the ad7790 has one differential analog input channel. this is connected to the on-chip buffer amplifier when the device is operated in buffered mode and directly to the modulator when the device is operated in unbuffered mode. in buffered mode (the buf bit in the mode register is set to 1), the input channel feeds into a high impedance input stage of the buffer amplifier. therefore, the input can tolerate significant source impedances and is tailored for direct connection to external resistive-type sensors such as strain gauges or resistance temperature detec- tors (rtds). when buf = 0, the part is operated in unbuffered mode. this results in a higher analog input current. note that this unbuffered input path provides a dynamic load to the driving source. therefore, resistor/capacitor combinations on the input pins can cause dc gain errors, depending on the output impedance of the source that is driving the adc input. table 16 shows the allowable external resistance/capacitance values for unbuffered mode such that no gain error at the 16-bit level is introduced. table 16. external r-c combination for no 16-bit gain error c (pf) r () 50 22.8 100 13.1 500 3.3 1000 1.8 5000 360 the absolute input voltage range in buffered mode is restricted to a range between gnd + 100 mv and v dd C 100 mv. care must be taken in setting up the common-mode voltage so that these limits are not exceeded. otherwise, there will be degrada- tion in linearity and noise performance. the absolute input voltage in unbuffered mode includes the range between gnd C 30 mv and v dd + 30 mv as a result of being unbuffered. the negative absolute input voltage limit does allow the possibility of monitoring small true bipolar signals with respect to gnd. programmable gain amplifier the output from the buffer on the adc is applied to the input of the on-chip programmable gain amplifier (pga). the pga gain range is programmed via the gain bits g1 and g0 in the mode register. ith an external 2.5 v reference applied, the pga can be programmed to have a bipolar range of 2.5 v, 1.25 v, 625 mv, or 312.5 mv. these are the ranges that should appear at the input to the on-chip pga. bipolar configuration the analog input to the ad7790 accepts a bipolar input voltage range. a bipolar input range does not imply that the part can tolerate negative voltages with respect to system gnd. bipolar signals on the ain(+) input are referenced to the voltage on the ain(C) input. for example, if ain(C) is 2.5 v and the adc is configured for a gain of 1, the analog input range on the ain(+) input is 0 v to 5 v. data output coding the output code is offset binary with a negative full-scale volt- age resulting in a code of 000...000, a ero differential input voltage resulting in a code of 100...000, and a positive full-scale input voltage resulting in a code of 111...111. the output code for any analog input voltage can be represented as code n ain gain v ref ere ain steaalotoltae gain stegaa ad n referencein eaasallderetaltcaaltorte caelecoooderaeortesederetalts srogntov ereerecetseredad tereoreecessercsorceedaceslltrodcea errorsereereceoltaerefinrefinrefins voalorsecedoeratotteasc toaltreereceoltaesrovtov ialcatos ereteectatooltaeorcrretortetrasdcero teaalotalsodrestereereceoltaeorteart teeectoteloreecoseteectatosorce llereoedecasetealcatosratoetrcite assedaoratoetrcalcatoaloose reerecesoldesed recoededvreereceoltaesorcesortea cldetearadarecaseteseareloose looerreerecesitecoleteaalosectosdre roavoersltereereceoltaesorcell reresoeeadrooitscaseavreerecescas tearorarsrecoededaalooselo oerreerecesalsootetattereerecetsrodea edacedacloadecasetetedaceo eacreerecetsdacresstorcaactorcoa tosotesetscacasedcaerrorsdeedote ottedaceotesorcetatsdrtereerece tsreereceoltaesorcesletoserecoeded aoeearlltcallaeloottedaces adaretereoretolerattoadecolcaactorso
ad7790 rev. 0 | page 18 of 20 refin(+) without introducing gain errors in the system. deriv- ing the reference input voltage across an external resistor will mean that the reference input sees a significant external source impedance. external decoupling on the refin pins would not be recommended in this type of circuit configuration. v dd monitor along with converting external voltages, the analog input chan- nel can be used to monitor the voltage on the v dd pin. when the ch1 and ch0 bits in the communications register are set to 1, the voltage on the v dd pin is internally attenuated by 5 and the resultant voltage is applied to the - modulator using an inter- nal 1.17 v reference for analog to digital conversion. this is useful because variations in the power supply voltage can be monitored. grounding and layout since the analog inputs and reference inputs of the adc are differential, most of the voltages in the analog modulator are common-mode voltages. the excellent common-mode rejec- tion of the part will remove common-mode noise on these inputs. the digital filter will provide rejection of broadband noise on the power supply, except at integer multiples of the modulator sampling frequency. the digital filter also removes noise from the analog and reference inputs, provided that these noise sources do not saturate the analog modulator. as a result, the ad7790 is more immune to noise interference than a con- ventional high resolution converter. however, because the resolution of the ad7790 is so high, and the noise levels from the ad7790 are so low, care must be taken with regard to grounding and layout. the printed circuit board that houses the ad7790 should be designed such that the analog and digital sections are separated and confined to certain areas of the board. a minimum etch technique is generally best for ground planes because it gives the best shielding. it is recommended that the ad 7790?s gnd pin be tied to the agnd plane of the system. in any layout, it is important that the user keep in mind the flow of currents in the system, ensur- ing that the return paths for all currents are as close as possible to the paths the currents took to reach their destinations. avoid forcing digital currents to flow through the agnd sections of the layout. the ad7790?s ground plane should be allowed to run under the ad7790 to prevent noise coupling. the power supply lines to the ad7790 should use as wide a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other sections of the board, and clock signals should never be run near the analog inputs. avoid crossover of digital and analog signals. traces on opposite sides of the board should run at right angles to each other. this will reduce the effects of feedthrough through the board. a microstrip technique is by far the best, but it is not always possible with a double-sided board. in this technique, the component side of the board is dedicated to ground planes, while signals are placed on the solder side. good decoupling is important when using high resolution adcs. v dd should be decoupled with 10 f tantalum in parallel with 0.1 f capacitors to gnd. to achieve the best from these decoupling components, they should be placed as close as possible to the device, ideally right up against the device. all logic chips should be decoupled with 0.1 f ceramic capacitors to dgnd.
ad7790 rev. 0 | page 19 of 20 outline dimensions 0.23 0.08 0.80 0.60 0.40 8 0 0.15 0.00 0.27 0.17 0.95 0.85 0.75 seating plane 1.10 max 10 6 5 1 0.50 bsc 3.00 bsc 3.00 bsc 4.90 bsc pin 1 coplanarity 0.10 compliant to jedec standards mo-187ba figure 11. 10-lead mini small outline package [msop] (rm-10) dimensions shown in millimeters esd (electrostatic discharge) sensitive device. electros tatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. table 17. ordering guide model temperature range package desc ription package option branding ad7790brm C40c to +105c 10-lead mini small outline package (msop) rm-10 cos AD7790BRM-REEL C40c to +105c 10-lead mini small outline package (msop) rm-10 cos
ad7790 rev. 0 | page 20 of 20 notes ? 2003 analog devices, inc. all rights reserved. trademarks and regis- tered trademarks are the property of their respective companies. c03538-0-8/03(0)

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